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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. 2.5a buck controller with integrated high-side mosfet ISL78205 the ISL78205 is a synchronous buck controller with a 90m ? high side mosfet and low side driver integrated. the ISL78205 supports a wide input voltage range from 3v to 40v. regarding the output current capability, the ISL78205 can typically support a continuous load of 2.5a under conditions of 5v v out , v in range of 8v to 30v, 500khz, +85c ambient temperature with still air. for any specific application, the actual maximum output curre nt depends upon the die temperature not exceeding +125c with the power dissipated in the ic, which is related to input voltage, output voltage, duty cycle, switching frequency, ambient temperature and board layout, etc. refer to ?output current? on page 12 for more details. the ISL78205 offers the most robust current protections. it uses peak current mode control with cycle-by-cycle current limiting. it is implemented with frequency foldback under current limit conditio ns. in addition, the hiccup overcurrent mode is also implemented to guarantee reliable operations under harsh short conditions. the ISL78205 has comprehensive protections against various faults, including overvoltage and over-temperature protections, etc. features ? ultra wide input voltage range 3v to 40v ? less than 3a standby input current (ic disabled) ? temperature range -40c to +105c ? integrated 90m ? high-side mosfet ? operational topologies -synchronous buck -non-synchronous buck ? programmable frequency from 200khz to 2.2mhz and frequency synchronization capability ? 1% tight voltage regulation accuracy ? reliable cycle-by-cycle overcurrent protection - temperature compensated current sense - frequency foldback - programmable oc limit -hiccup mode protection in worst case short condition ? 20 ld htssop package ? pb-free (rohs compliant) applications ? automotive applications ? general purpose power regulator ? 24v bus power ?battery power ? embedded processor and i/o supplies figure 1. typical application schematic i - synchronous buck v out ISL78205 vcc sgnd boot vin phase pgnd dgnd fs en fb comp v in lgate ilimit ss sync pgood 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 2.5 figure 2. efficiency, synchronous buck, 500khz, v out 5v, t a = +25c load current (a) efficiency (%) 40v 6v 12v 24v september 22, 2011 fn7926.0 www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 2 fn7926.0 september 22, 2011 pin configuration ISL78205 (20 ld htssop) top view functional pin description pin name pin # description pgnd 1 this pin is used as the ground connection of the power flow, including the driver. boot 2 this pin provides bias voltage to the high-side mosfet driv er. a bootstrap circuit is used to create a voltage suitable to drive the internal n-channel mosfet. the boot char ge circuitries are integrated inside of th e ic. no external boot diode is needed. a 1f ceramic capacitor is recommended to be used between the boot and phase pin. vin 3, 4 connect the input rail to these pins that are connected to the drain of the in tegrated high-side mosfet, as well as the source for the internal linear regulator that provides the bias of the ic. with the part switching, the operating in put voltage applied to the vin pins must be under 40v. this recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding absolute maximum ratings. sgnd 5 this pin provides the return path for the control and monitor portions of the ic. vcc 6 this pin is the output of the intern al linear regulator that supp lies the bias for the ic, incl uding the driver. a minimum 4.7f decoupling ceramic capacitor is recommended between vcc to ground. en 8 the controller is enabled when this pin is pulled high. the ic is disabled when this pin is pulled low. range: 0v to 5.5v. fs 9 tying this pin to vcc, or gnd, or leav ing it open will force the ic to have 500k hz switching frequency. the oscillator switc hing frequency can also be programmed by adjust ing the resistor from this pin to gnd. ss 10 connect a capacitor from this pin to ground. this capacitor, along with an internal 5a current source, sets the soft-start interval of the converter. also, this pin can be used to track a ramp on this pin. fb 11 this pin is the inverting input of the voltage feedback error amplifier. with a pr operly selected resistor divider connecte d from v out to fb, the output voltage can be set to any voltage betwee n the input rail (reduced by maximum duty cycle and voltage drop) and the 0.8v reference. loop compensation is achieved by connecting an rc network across comp and fb. the fb pin is also monitored for overvoltage events. comp 12 output of the voltage feedback error amplifier. ilimit 13 programmable current limit pin. with this pin connected to vcc pin, or to gn d, or left open, the current limit threshol d is set to a default of 3.6a; the current limit threshold can be programmed with a resistor from this pin to gnd. dgnd 14 digital ground pin. connect to sgnd at quiet ground copper plane. pgood 15 pgood is an open drain output that will be pulled low imme diately in the event that the ou tput is out of regulation (ov or uv) or the en pin is pulled low. pgood is equipped with a fixed delay of 1000 cycles upon output power-up (v o > 90%). phase 16, 17 these pins are the phase nodes that should be connec ted to the output inductor. these pins are connected to the sour ce of the high side n-channel mosfet. sync 19 this pin can be used to synchronize two or more ISL78205 controllers. multiple ISL78205s can be synchronized with their sync pins connected together. 180 degree phase shift is automatically generated between the master and slave ics. the internal oscillator can also lock to an external frequency source applied to th is pin with square pulse waveform (with frequency 10% higher than the ic?s local freq uency, and pulse width higher than 150ns). this pin should be left floating if not used. 21 pad nc phase pgood dgnd ilimit fb phase comp 11 12 13 14 15 16 17 18 lgate sync 19 20 pgnd boot vin vin sgnd vcc nc en fs ss 1 2 3 4 5 6 7 8 9 10 www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 3 fn7926.0 september 22, 2011 lgate 20 in synchronous buck mode, this pin is used to drive the lower side mosfet to improve efficiency. in non-synchronous buck when a diode is used as the bottom si de power device, this pin should be connected to vcc before vcc start-up to disable the low side driver (lgate). nc 7, 18 no connection pin. connect these pins to sgnd at quiet ground copper plane. pad 21 bottom thermal pad. it is not connected to any electrical potential of the ic. in la yout, it must be connected to pcb ground copper plane with area as large as possible to effectively reduce the thermal impedance. functional pin description (continued) pin name pin # description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL78205avez 78205 avez -40 to +105 20 ld htssop mdp0048 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL78205 . for more information on msl please see techbrief tb363 . www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 4 fn7926.0 september 22, 2011 block diagram pgood ss fb boot phase (x2) current monitor sgnd en fs comp vcc vin 0.8v reference voltage monitor vin (x2) vcc pgnd control logic ocp, ovp, otp slope compensation lgate ilimit ea comparator oscillator vcc 5 a + + power-on reset soft-start logic sync gate drive bias ldo boot refresh www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 5 fn7926.0 september 22, 2011 typical application schema tic i - synchronous buck typical application schemat ic ii - non-synchronous buck v out ISL78205 vcc sgnd boot vin phase pgnd dgnd fs en fb comp v in lgate ilimit ss sync pgood v out ISL78205 vcc sgnd boot vin phase pgnd dgnd fs en fb comp v in lgate ilimit ss sync pgood www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 6 fn7926.0 september 22, 2011 absolute maximum rating s thermal information vin, phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +44v vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +6.0v absolute boot voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0v upper driver supply voltage, v boot - v phase . . . . . . . . . . . . . . . . . . . +6.0v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to vcc + 0.3v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000v latch up rating (tested per jesd78b; class ii, level a) . . . . . . . . . 100ma recommended operating conditions supply voltage on vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 40v ambient temperature range (automotive). . . . . . . . . . . . . . .-40c to +105c junction temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c thermal resistance ja (c/w) jc (c/w) 20 ld htssop package (notes 4, 5) . . . . . . . 32 3.5 maximum junction temperature (plastic package) . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications refer to ?block diagram? on page 4 and typica l application schematics on page 5. operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v, t a = -40c to +105c. typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. parameter symbol test conditions min (note 7) typ max (note 7) units v in supply v in voltage range v in 3.05 40 v v in connected to vcc 3.05 5.5 v operating supply current i q no switching 1.2 ma standby supply current i q_sby en connected to gnd, v in = 12v 1.8 3 a internal main linear regulator main ldo v cc voltage v cc v in > 5v 4.2 4.5 4.8 v main ldo dropout voltage v dropout_main v in = 4.2v, i vcc = 35ma 0.3 0.5 v v in = 3v, i vcc = 25ma 0.25 0.3 v v cc current limit of main ldo 60 ma power-on reset rising v cc por threshold v porh_rise 2.82 2.9 3.05 v falling v cc por threshold v porl_fall 2.6 2.8 v v cc por hysteresis v porl_hys 0.3 v enable required enable on voltage v enh 2 v required enable off voltage v enl 0.8 v www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 7 fn7926.0 september 22, 2011 oscillator pwm frequency f osc r t = 665k ? 160 200 240 khz r t = 51.1k ? 1950 2200 2450 khz fs pin connected to vcc or floating or gnd 450 500 550 khz min on time t min_on 130 225 ns min off time t min_off 210 325 ns reference voltage reference voltage v ref 0.8 v system accuracy -1.0 1.0 % fb pin source current 5na soft-start soft-start current i ss 3 5 7 a error amplifier unity gain-bandwidth c load = 50pf 10 mhz dc gain c load = 50pf 88 db maximum output voltage 3.6 v minimum output voltage 0.5 v slew rate sr c load = 50pf 5 v/s internal high-side mosfet upper mosfet r ds(on) r ds(on)_up note 6 90 150 m ? low-side mosfet gate driver lgate source resistance 100ma source current 3.5 ? lgate sink resistance 100ma sink current 3.3 ? power good monitor overvoltage rising trip point v fb /v ref percentage of reference point 104 110 116 % overvoltage rising hysteresis v fb /v ovtrip percentage below ov trip point 3 % undervoltage falling trip point v fb /v ref percentage of reference point 84 90 96 % undervoltage falling hysteresis v fb /v uvtrip percentage above uv trip point 3 % pgood rising delay t pgood_delay f osc = 500khz 2 ms pgood leakage current pgood high, v pgood = 4.5v 10 na pgood low voltage v pgood pgood low, i pgood = 0.2ma 0.10 v overcurrent protection default cycle by cycle current limit threshold i oc_1 ilimit = gnd or vcc or floating 3 3.6 4.2 a hiccup current limit threshold i oc_2 hiccup, i oc_2 /i oc_1 115 % overvoltage protection ov latching-off trip point percentage of reference point lg = ug = latch low 120 % electrical specifications refer to ?block diagram? on page 4 and typica l application schematics on page 5. operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v, t a = -40c to +105c. typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 8 fn7926.0 september 22, 2011 ov non-latching-off trip point percentage of reference point lg = ug = low 110 % ov non-latching-off release point p ercentage of reference point 102.5 % over temperature protection over-temperature trip point 155 c over-temperature recovery threshold 140 c note: 6. wire bonds not included. th e wire bond resistance between vin and phase pin is 32m ? typical. 7. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications refer to ?block diagram? on page 4 and typica l application schematics on page 5. operating conditions unless otherwise noted: v in = 12v, or v cc = 4.5v, t a = -40c to +105c. typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 9 fn7926.0 september 22, 2011 typical performance curves figure 3. efficiency, synchronous buck, 500khz, v out 5v, t a = +25c figure 4. efficiency, synchronous buck, 500khz, v out 3.3v, t a = +25c figure 5. load regulation, v out 5v, t a = +25c figure 6. line regulation, v out 5v, t a = +25c figure 7. ic die temperature under +25c ambient temperature, still air, 500khz, i o = 2a figure 8. ic die temperat ure under +25c ambient temperature, still air, 500khz, v out = 5v 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.00.51.01.52.02.5 load current (a) efficiency (%) 40v 6v 12v 24v 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 2.5 load current (a) efficiency (%) 40v 6v 12v 24v 4.950 4.952 4.954 4.956 4.958 4.960 4.962 4.964 4.966 4.968 4.970 0.0 0.5 1.0 1.5 2.0 2.5 load current (a) v out (v) 40v 6v 12v 24v 4.950 4.952 4.954 4.956 4.958 4.960 4.962 4.964 4.966 4.968 4.970 0 5 10 15 20 25 30 35 40 45 50 input voltage (v) v out (v) i o = 0a i o = 2a i o = 1a 25 30 35 40 45 50 55 60 65 70 75 80 85 0 5 10 15 20 25 30 35 40 45 50 v in (v) ic die temperature (c) v out = 5v v out = 12v v out = 20v 25 30 35 40 45 50 55 60 65 70 75 80 85 1.0 1.5 2.0 2.5 i out (a) ic die temperature (c) v in = 24v v in = 12v v in = 6.5v v in = 40v www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 10 fn7926.0 september 22, 2011 figure 9. v in 36v, pre-biased start-up figure 10. synchronous buck mode, v in 36v, i o 2a, enable on figure 11. synchronous buck, v in 36v, i o 2a figure 12. synchronous buck mode, v in 36v, i o 2a, enable off figure 13. v in 24v, 0a to 2a step load figure 14. non-synchronous buck, force pwm mode, v in 12v, no load typical performance curves (continued) v out 2v/div 2ms/div phase 20v/div v out 2v/div 2ms/div phase 20v/div v out 20mv/div (5v offset) phase 20v/div 5s/div v out 2v/div 2ms/div phase 20v/div v out 100mv/div (5v offset) i out 1a/div phase 20v/div 1ms/div v out 10mv/div (5v offset) phase 5v/div 20s/div www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 11 fn7926.0 september 22, 2011 figure 15. non-synchronous buck, force pwm mode, v in 12v, 2a typical performance curves (continued) v out 10mv/div (5v offset) phase 10v/div 5s/div www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 12 fn7926.0 september 22, 2011 functional description initialization initially, the ISL78205 continually monitors the voltage at the en pin. when the voltage on the en pin exceeds its rising threshold, the internal ldo will start-up to build up vcc. after power-on reset (por) circuits detect that the vcc voltage has exceeded the por threshold, the soft-start will be initiated. soft-start the soft-start (ss) ramp is built up in the external capacitor on the ss pin that is charged by an internal 5a current source. the ss ramp starts from 0 to voltage above 0.8v. once ss reaches 0.8v, the bandgap reference takes over and ic gets into steady state operation. the ss plays a vital role in the hiccup mode of operation. the ic works as cycle-by-cycle peak current limiting at over load condition. when a harsh condition occurs and the current in the upper side mosfet re aches the second overcurrent threshold, the ss pin is pulled to ground and a dummy soft-start cycle is initiated. at dummy ss cycle, the current to charge the soft-start cap is cut down to 1/5 of its normal value. therefore, a dummy ss cycle takes 5 times that of th e regular ss cycle. during the dummy ss period, the control loop is disabled and there is no pwm output. at the end of this cy cle, it will start the normal ss. the hiccup mode persists until the second overcurrent threshold is no longer reached. the ISL78205 is capable of starting up with pre-biased output. pwm control the ISL78205 employs the peak current mode pwm control for fast transient response and cycl e-by-cycle current limiting. see the ?block diagram? on page 4. the pwm operation is initialized by the clock from the oscillator. the upper mosfet is turned on by the clock at the beginning of a pwm cycle and the current in th e mosfet starts to ramp up. when the sum of the current sense signal and the slope compensation signal reaches the error amplifier output voltage level, the pwm comparator is triggered to shut down the pwm logic to turn off the high side mosfet. the high side mosfet stays off until the next clock signal starts. the output voltage is sensed by a resistor divider from v out to fb pin. the difference between the fb voltage and 0.8v reference is amplified and compensated to generate the error voltage signal at the comp pin. then the comp pin signal is compared with the current ramp signal to shut down the pwm. synchronous and non-synchronous buck the ISL78205 supports both synchronous and non-synchronous buck operations. for a non-synchronous buck operation when a power diode is used as the low side power device, the lgate driver can be disabled with lgate connected to vcc (before ic start-up). input voltage with the part switching, the op erating input voltage applied to the vin pins must be under 40v. this recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding absolute maximum ratings. output voltage the ISL78205 output voltage can be programmed down to 0.8v by a resistor divider from v out to fb. the maximum achievable voltage is (v in *d max -v drop ), where v drop is the voltage drop in the power path, includ ing mainly the mosfet r ds(on) and inductor dcr. the maximum duty cycle d max is decided by (1/fs - t min_off ). output current with the high side mosfet integrated, the maximum current that the ISL78205 can support is decided by the package and many operating conditions, including input voltage, output voltage, duty cycle, switching frequency and temperature, etc. first, the maximum dc output current is 5a limited by the package. second, from the thermal perspective, the die temperature shouldn?t be above +125c with the power loss dissipated inside of the ic. figures 7 and 8 show the thermal performance of this part operating at different conditions. figure 7 shows 2a applications under +25c still air conditions. different v out (5v, 12v, 20v) applications thermal data are shown over v in range at +25c and still air. the temperature rise data in this figure can be used to estimate the die temperature at different ambient temperatures under various operat ing conditions. note that more temperature rise is expected at higher ambient temperature due to more conduction loss caused by r ds(on) increase. figure 8 shows 5v output applications' thermal performance under various output current and input voltage. it shows the temperature rise tren d with load and v in changes. the part can output 2.5a under typical application conditions (v in 8~30v, v out 5v, 500khz, still air and +85 c ambient conditions). the output current should be derated under any conditions, causing the die temperature to exceed +125c. basically, the die temperature is equal to the sum of the ambient temperature and the temperature rise resulting from the power dissipated from the ic package with a certain junction to ambient thermal impedance ja . the power dissipated in the ic is related to the mosfet switch ing loss, conduction loss and the internal ldo loss. besides the load, these losses are also related to input voltage, output voltage, duty cycle, switching frequency and temperature. with the exposed pad at the bottom, the heat of the ic mainly goes through the bottom pad and ja is greatly reduced. the ja is highly related to layout and air flow conditions. in layout, multiple vias ( 15) are strongly recommended in the ic bottom pa d. in addition, the bottom pad with its vias should be placed in the ground copper plane with an area as large as possible connected through multiple layers. the ja can be reduced further with air flow. with 100cfm air flow, the ja can be reduced by 25%. c ss f [] 6.5 t ss s [] ? = (eq. 1) www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 13 fn7926.0 september 22, 2011 oscillator and synchronization the oscillator has a default freq uency of 500khz with the fs pin connected to vcc, or ground, or floating. the frequency can be programmed to any frequency be tween 200khz and 2.2mhz with a resistor from the fs pin to gnd. with the sync pins simply connected together, multiple ISL78205s can be synchronized. the slave ics automatically have 180 degree phase shift with respect to the master ic. with an external square puls e waveform (with frequency 10% higher than the local frequency, 10% to 90% duty cycle and pulse width higher than 150ns) on th e sync pin, the ISL78205 will synchronize its switching frequency to the fundamental frequency of the input waveform. the internal oscillator synchronizes with the leading edge of the input signal. the rising edge of ugate pwm is delayed by 180 degrees from the leading edge of the external clock signal. fault protection overcurrent protection the overcurrent function protects against any overload conditions and output shorts at worst case, by monitoring the current flowing through the upper mosfet. there are 2 current limiting thresholds. the first one, i oc1 , is to limit the high-side mosfet peak current cycle-by-cycle. the current limit threshold is set to a default of 3.6a with the ilimit pin connected to gnd or vcc, or left open. the current limit threshold can also be pr ogrammed by a resistor r lim at ilimit pin to ground. use equation 3 to calculate the resistor. note that with the lower r lim , ioc1 is higher. ioc1 reaches its maximum 5.4a with r lim at 54.9k (typ). with r lim lower than 54.9k (typ), the oc limit goes to its default value of 3.6a (typ). the second current protection threshold, i oc2 , is 15% higher than i oc1 mentioned above. upon the instant that the high-side mosfet current reaches i oc2 , the pwm shuts off after 2 cycle delay and the ic enters hiccup mode. in hiccup mode, the pwm is disabled for dummy soft-start duration equaling 5 regular soft-start periods. after this du mmy soft-start cycle, the true soft-start cycle is attempted again. the i oc2 offers a robust and reliable protection against worst case conditions. the frequency fold ba ck is implemented for the ISL78205. when overcurrent limiting, the switching frequency is reduced to be proportional to the output voltage in order to keep the inductor current under limit threshold during overload conditions. the low limit of frequency under frequency foldback is 40khz. overvoltage protection if the voltage detected on the fb pin is over 110% of reference, the high-side and low-side driv er shuts down immediately and will not be allowed to turn on until the fb voltage falls down to 0.8v. when the fb voltage drops to 0.8v, the drivers are released on. if the 120% overvoltage thre shold is reached, the high-side and low-side driver shut down immediately and the ic is latched off. the ic has to be reset for restart. thermal protection the ISL78205 pwm will be disabled if the juncti on temperature reaches +155c. a +15c hysteresis insures that the device will not restart until the junction temperature drops below +140c. component selection output capacitors output capacitors are required to filter the inductor current and supply the load transient current. all ceramic output capacitors are achievable with this ic. also, in applications the aluminum electrolytic type capacitor provides better load transient and longer holdup time for the load. when low cost, high esr aluminum capa citors are used at the output. ceramic capacitors (2.2f to 10f) are recommended to handle the ripple current and reduce the total equivalent esr effectively. r fs k [] 145000 16 fs ? khz [] ? fs khz [] ------------------------------------------------------------- - = (eq. 2) figure 16. r fs vs frequency 0 200 400 600 800 1000 1200 0 500 1000 1500 2000 2500 f s (khz) r fs (k ? ) r lim 300000 i oc a [] 0.018 + -------------------------------------- - = (eq. 3) figure 17. r lim vs ioc1 i oc1 (a) r lim (k ? ) 70 120 170 220 270 320 370 0123456 www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 14 fn7926.0 september 22, 2011 input capacitors depending upon the system input power rail conditions, the aluminum electrolytic type capacitor is normally needed to provide the stable input voltag e and restrict the switching frequency pulse current in small areas over the input traces for better emc performance. the input capacitor should be able to handle the rms current from the switching power devices. ceramic capacitors must be used at the vin pin of the ic and multiple capacitors, including 1f and 0.1f, are recommended. place these capacitors as closely as possible to the ic. output inductor generally the inductor should filter the current ripple to be 30~40% of the regulator?s maximum average output current. the low dcr inductor should be selected for the highest efficiency. in addition, the inductor saturation current rating should be higher than the highest transient expected. low side power mosfet in synchronous buck applications, a power n mosfet is needed as the synchronous low side mosfet and it must have low r ds(on) , lowest rg (rg_typ < 1.5 ? recommended ) , vgth (vgth_min 1.2v) and qgd. a good example is bsz100n06ls3g. output voltage feedback resistor divider the output voltage can be programmed down to 0.8v by a resistor divider from v out to fb, according to equation 4. in applications requiring the le ast input quiescent current, large resistors should be used for th e divider to keep its leakage current low. 232k is a recommended for the upper resistor. compensation network with peak current mode control, type ii compensation is normally used for most applicat ions. however, in applications seeking achieve higher bandwidth, type iii compensation is good to use. layout suggestions 1. place the input ceramic capacitors as close as possible to the ic vin pin and power ground conne cting to the power mosfet or diode. keep this loop (input ceramic capacitor, ic vin pin and mosfet/diode) as tiny as possibl e to achieve the least voltage spikes induced by the trace parasitic inductance. 2. place the input aluminum capacitors close to the ic vin pin. 3. keep the phase node copper area small, but large enough to handle the load current. 4. place the output ceramic and aluminum capacitors also close to the power stage components. 5. put vias ( 15) in the bottom pad of the ic. the bottom pad should be placed in the ground copper plane with area as large as possible in multiple layers to effectively reduce the thermal impedance. 6. place the 4.7f ceramic decoupling capacitor at the vcc pin and as close as possible to the ic. put multiple vias ( 3) close to the ground pad of this capacitor. 7. keep the bootstrap capacitor close to the ic. 8. keep the lgate drive trace as short as possible and try to avoid using via in lgate drive path to achieve the lowest impedance. 9. place the positive voltage sense trace close to the load for tighter regulation. 10. put all the peripheral control components close to the ic. v out 0.8 1 r up r low --------------- + ?? ?? ?? ? = (eq. 4) figure 18. pcb via pattern www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 15 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7926.0 september 22, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL78205 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change september 22, 2011 fn7926.0 initial release www.datasheet.co.kr datasheet pdf - http://www..net/
ISL78205 16 fn7926.0 september 22, 2011 htssop (heat-sink tssop) family n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane bottom view exposed thermal pad e2 d1 mdp0048 htssop (heat-sink tssop) family symbol millimeters tolerance 14 ld 20 ld 24 ld 28 ld 38 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.075 0.075 0.075 0.075 0.075 0.075 a2 0.90 0.90 0.90 0.90 0.90 +0.15/-0.10 b 0.25 0.25 0.25 0.25 0.22 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 6.50 7.80 9.70 9.70 0.10 d1 3.2 4.2 4.3 5.0 7.25 reference e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e2 3.0 3.0 3.0 3.0 3.0 reference e 0.65 0.65 0.65 0.65 0.50 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference n 1420242838reference rev. 3 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994. www.datasheet.co.kr datasheet pdf - http://www..net/

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